[Oberon] Unlimited Oberon System for any board

Guy T. turgu666 at gmail.com
Sun May 10 00:05:37 CEST 2020

Hello Wojtek,

I had a closer look to the HF-RISC-V and I can confirm that it implements all “The RISC-V” basic integer instructions. No options have been implemented. That means no Integer Multiplication/Division, no compressed instructions, no floating point, etc. There is some code related to multiplication but from the comments it seems that it was not integrated and may not be complete. I found very interesting how the VHDL code was structured.

This implementation would certainly be useful for some usage, but without some of the options, I don’t known if it could be considered to implement Project Oberon with it.

This is my own observation, as a newbie with FPGAs. So this must be confirmed by some better expert than me!


>> What about using RISC-V ISA on FPGA, allowing for “some kind of” easy path between RISC-V chips and FPGA made systems?
>Have a look at 
>http://opencores.org/project,hf-risc   (older version)
>https://github.com/sjohann81/hf-risc (newer version)
>The older version from Open Cores runs on the same Spartan-3 starter kit which originally hosted RISC5. The newer >version removed that support and added some other stuff. The highlights which are worth exploring:
>1. The project is mostly in VHDL which I like much better than NW Verilog. 
>2. The structure of the HF-RISC-V seems more clear to me than RISC5, which is IMHO too terse with too few comments (ETH >specialty, I guess). 
>3. The HF CPU is explicitly pipelined and there is some discussion. The discussion is a little bit above my head, but at >least there is hope of understanding.
>4. There is also a MIPS variant in the same archive. It may be interesting to compare the three approaches, HF-RISC-V, >MIPS, and RISC5. 
>Please note that this is "a RISC-V" rather than "the RISC-V". I am not sure what is the connection between *this* RISC-V >and the official one. I suspect that just like there is no "the ARM", there is no such thing as "the RISC-V" either.
>Hope it helps,

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