[Oberon] Project Oberon running from LPDDR memory on Pipistrello

[Magnus Karlsson]

The project have been updated at 
https://github.com/Saanlima/Pipistrello/tree/master/Projects/Oberon_lpddr
This version is based on the current RISC5 verilog code (dated 11.12.2018).

System info:
Cache size: 128 KB (2-way 256-set).
Cached area: lower 15.75 MB of the RISC5 memory map is mapped to 
cache/lpddr memory.
The non-cached area (top 256 KB of the RISC5 memory map) is used for I/O 
(top 4KB), boot prom (next 4KB), then a free 248 KB area where the video 
display buffer can be relocated .
Video buffer is in BRAM and is located at the default place at power up 
but can be relocated anywhere in the memory map by simply writing to a 
new 24-bit video base register.
Since the video frame buffer is in non-cached BRAM there is no need to 
flush the cache, which btw uses write-back policy.
The system will be slowed down by cache misses but there is about 11% 
gain by having the video buffer in BRAM (no cpu stalls due to video 
controller memory access).

Magnus

On 5/11/2020 7:01 AM, Magnus Karlsson wrote:
> Oh, so it is/was a bug in the risc5 verilog code.
>
> I actually got the RISC5 source code from emard 
> (https://github.com/emard/oberon) where the cpu clock enable signal 
> was added.
> I agree, updating to the latest version would be good.  I will pick it 
> up from Project Oberon and create a new bit file.
>
> Magnus
>
>
> On 5/11/2020 1:37 AM, Paul Reed wrote:
>> Hi Joerg, Magnus,
>>
>> Surely that's to do with data access not jumps?  But anyway, I 
>> believe updating the Verilog will indeed fix the 2MB problem, it did 
>> for me.  I think the bug you found was to do with type descriptor 
>> access off a pointer, which was fixed a while back. Apologies for this!
>>
>> Hope that helps - and thanks for your efforts!
>> Paul
>>
>>
>>
>> On 2020-05-11 09:31, Jörg Straube wrote:
>>> Magnus
>>>
>>> Don’t know if this is the culprit:
>>>
>>> There was this line in the RISC5.v you used:
>>>
>>> assign adr = stallL ? B[23:0] + {4'b0, off} : {pcmux, 2'b00};
>>>
>>> For backward jumps this would be better
>>>
>>> assign adr = stallL ? B[23:0] + {{4{off[19]}}, off} : {pcmux, 2'b00};
>>>
>>> I’m in the process to verify and will include the newest
>>> enhancements and bug fixes in the Verilog files. (rounding error in
>>> floating points, new shifter and registers…) and compiler.
>>>
>>> br
>>>
>>> Jörg
>
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