[Oberon] PO2013 - SD Image Tool

[Jörg]

Look at the schematic http://www.saanlima.com/download/pepino-v1.1/pepino4-schematic.pdf
The FTDI is the block called "U7" on slide 2.
Pin 40 and PIN 41 are RTS and CTS

Now, if you scroll to page 4 you see the four columns called U4B0..U4B4; these are all pins of the FPGA
Look at U4B1, there you see that FPGA pin C15 is RTS and Pin 16 is CTS. These two are connected to the FTDI pins mentioned above.

But the pins C15 and C16 are not mapped to Oberon signals. The mapping of the pins to Verilog signals is done in the ucf file:
https://github.com/Saanlima/Pepino/blob/master/Projects/RISC5Verilog_Pepino/src/RISC5_pepino.ucf

br
Jörg


Am 22.05.20, 20:49 schrieb "Oberon im Auftrag von Tomas Kral" <oberon-bounces at lists.inf.ethz.ch im Auftrag von thomas.kral at email.cz>:

    Hi Joerg,
    
    > The FTDI can deliver HW flow control signals RTS/CTS.
    > Magnus even connected them to the FPGA. Look at the schematic.
    
    For the time being I would be at least happy to recognise FTDI block in
    the wiring :-) I can only see Spartan6 FPGA, that is a big square.
    
    > It would be a nice little task to enable CTS/RTS in Oberon. Perhaps
    > have a try. You have to modify the UCF
    > You have to modify RISC5Top.v
    > You have to modify the serial drivers in Oberon
    
    That is generous.
    When I gather more skills with Verilog (reading Pong's book).
    
    These signals could be routed to GPIO?
    
    USB is packet based, cannot imagine a driver dealing with
    RTS/CTS hidden inside some data packets.
    
    Meanwhile I can live with a small delay in OCR.OR Loop.
    File transfer works, seems, I do hope. 
    
    -- 
    Tomas Kral <thomas.kral at email.cz>
    --
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