[Oberon] Interrupt latency of RISC5?

[Skulski, Wojciech]

Hi:

Does anyone know what is the interrupt serving latency of the new RISC5 described in "An Update of the RISC5 Implementation", Niklaus Wirth, 15.6.2018? How many clock cycles are needed before the CPU executes the first instruction of the ISR?  

It is not stated in the paper, or at least I cannot decipher the info. The timing diagram on page 3 is not complete because the clock signal is not plotted. It is thus not clear whether this figure is a specification to be relied upon, or merely a conceptual diagram for illustration of various signals. 

Thanks!
Wojtek