[Oberon] Interrupt latency of RISC5?

Hellwig Geisse hellwig.geisse at mni.thm.de
Sat Jun 6 17:10:12 CEST 2020


On Sa, 2020-06-06 at 13:20 +0000, Skulski, Wojciech wrote:
> Does anyone know what is the interrupt serving latency of the new RISC5 described in "An Update of
> the RISC5 Implementation", Niklaus Wirth, 15.6.2018? How many clock cycles are needed before the
> CPU executes the first instruction of the ISR?  

your question can be understood in two different ways:

1. What interrupt serving latency is specified in the paper?
2. What interrupt serving latency does NW's implementation show?

The second question is easy: 2 clock cycles plus any delays coming
from memory stalls (irq rising to intPnd: max. 1 cycle, intPnd to
intAck: 0 cycles - but this can be elongated by stallr, intAck to
pcmux: 0 cycles, pcmux to fetch from address 4: 1 cycle).

The strict answer to the first question is "this is not specified"
because the status of the implementation given is not clear. Is it
a reference implementation? I guess (in accordance with so many other
answers I've read in this mailing list), that the exact specification
is intendedly left open.


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