[Oberon] Re (2): Fixup documentation; was: Documentation;

[Paul Reed]

Hi Lyall,

> The discusion of instructions prompted me to wonder why RISC-Arch.pdf
> doesn't specify syntax of instructions by EBNF.

It is a conscious choice to avoid an assembler syntax and formal 
mnemonics for RISC5. In the preface to the FPGA version of Project 
Oberon, Prof. Wirth writes

   "A welcome consequence of the simplifications of language and 
processor is the fact that all parts that had been written in assembler 
code in 1992 -- and therefore were not included in the book -- have now 
been expressed in Oberon as well. Vindicating my perennial efforts to 
obtain a high-level language which is powerful and flexible, and also 
efficient enough to express parts such as device drivers and raster 
operations, this was the necessary and final step to make this book 
comprehensive and complete."

Cheers
Paul