[Oberon] Re (2): Fixup documentation; was: Documentation;

peter at easthope.ca peter at easthope.ca
Sat Dec 19 01:00:53 CET 2020

From:	Hellwig Geisse <hellwig.geisse at mni.thm.de>
Date:	Fri, 18 Dec 2020 00:51:41 +0100
> Hope that helps - sorry for the rather brief explanation.

Definitely helps.  Thanks.

I know nothing about Verilog beyond the introductory paragraph at 
https://en.wikipedia.org/wiki/Verilog .  Learning it would be 
interesting and valuable; probably an unwise digression at present.

The notes about fixup should be more coherent now.  
https://en.wikibooks.org/wiki/Oberon/V5  Still not completely 
satisfactory.  Comments and criticism welcome.  Feel free to edit.

The discusion of instructions prompted me to wonder why RISC-Arch.pdf 
doesn't specify syntax of instructions by EBNF.  It's standard practice for 
the Oberon source languages.

Thanks again,                                ... L.

Tel: +1 604 670 0140            Bcc: peter at easthope. ca

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