[Oberon] RISK-V RV32IM

[Rikke Solbjørg]

Hi,

Yes, RV32IM is the compiler's target processor. RV simply means RISC-V, 
32 means 32-bit, I is the base instruction set containing fundamental, 
necessary instructions, and M is a small extension that adds 
instructions for multiplication and division.

You could quite easily get floating-point by adding the F extension, or 
with software emulation. If you add the F extension, you could implement 
it very similarly to how it is implemented in ORG.Mod. I decided against 
adding the F extension to the target processor, as it wasn't necessary 
to get Oberon running, and it would mean having to use a larger core for 
the FPGA to support it. I might add floating-point emulation, but it's 
pretty low on my priority list at the moment.

Also, the rows in the table are good, thank you for adding it! I added 
the "ø" in my last name; it's not on most keyboards :)

Cheers,

Rikke