[Oberon] Oberon V4 on the Raspberry Pi?

[Chris Burrows]

> -----Original Message-----
> From: Oberon [mailto:oberon-bounces at lists.inf.ethz.ch] On Behalf Of
> Bernhard Treutwein
> Sent: Tuesday, 12 January 2021 2:35 AM
> To: ETH Oberon and related systems
> Subject: Re: [Oberon] Oberon V4 on the Raspberry Pi?
> 
> 
> > Liam Proven <lproven at gmail.com> hat am 11.01.2021 16:50
> geschrieben:
> >
> >
> [...]
> >
> > So, if I have this straight now, Native Oberon (which _does_ run on
> > PCs and in a VM) is Oberon v3, but Oberon v4, AKA Linz Oberon,
> _only_
> > runs under Windows, Linux or macOS, not on hardware?
> >
> 
> Native Oberon was one platform of S3 (it was never called V3) and
> later renamed to ETH-Oberon. There were others running emulated under
> Windows, MacOS and Linux and revived by Peter Matthias as OLR ...
> 
> Oberon V4, aka Linz Oberon was never running on bare hardware (except
> Ceres) but emulated on top of MS-Windows, Solaris (68K and Sparc),
> HP-UX, Irix, Amiga, OS2 ...
> 

This is potentially confusing now that 'emulators' for Project Oberon exist.
They are different beasts altogether. Further to Paul's comments, at the
risk of being picky I would rephrase what you said as:

"Native Oberon is one platform of what was originally called Oberon System 3
(S3 - it was never called V3) and was later renamed to ETH-Oberon. There are
others hosted on Windows, MacOS and Linux and revived by Peter Matthias as
the Oberon Linux Revival (OLR) ...

Oberon V4, aka Linz Oberon only runs on bare hardware on the ETH Ceres
computer (which uses the National Semiconductor NS32xxx CPU) but is also
hosted on MS-Windows, Solaris (68K and Sparc), HP-UX, Irix, Amiga, OS2 ..."

My main point is that none of these systems are 'emulated'. In every case
instructions generated by the Oberon compiler are natively executed by the
CPU on the target platform.

On the other hand, AFAIK, currently all versions of Project Oberon running
on Windows, MacOS, Linux etc. ARE emulated. In this case, the compiler
generates RISC5 instructions that are then 'interpreted' by a software
emulation of the RISC5 CPU. Each RISC5 instruction results in tens
(hundreds?) of Intel (or whatever CPU is being used to run the OS) CPU
instructions being executed.

Note that Project Oberon running on FPGA hardware is not emulated. Every
RISC5 instruction generated by the compiler is executed directly by the
RISC5 CPU implemented in configurable hardware.

It's as clear as mud ... ;-)

Cheers,
Chris Burrows
CFB Software
https://www.astrobe.com/RISC5