[Oberon] RISC5: memory instructions and flags
hellwig.geisse at mni.thm.de
Sat Feb 6 13:46:42 CET 2021
I'm currently testing my re-implementation of the RISC5
system, which I carefully constructed to be consistent
with its defining paper "The RISC Architecture"
This document doesn't say anything about setting the condition
flags when executing memory instructions. Consequently, my
design of the CPU does not touch the flags during load and
store instructions [*].
As it turns out, this does not work with the current Oberon
compiler. Let "run" be a BOOLEAN variable. Then the condition
within the statement "IF run THEN ..." is compiled to
which only is correct if LDB sets the zero flag according to
the data loaded. NW's RISC5 implementation does exactly that.
Now, who is right? May the compiler rely on the fact that
the condition flags are set on a load? Then the definition
of the RISC5 instruction set must be changed. Or is the CPU
entitled to load data without setting the flags? Then the
compiler must be updated.
[*] Setting the flags during load/store instructions is
*very* unusual in RISC designs because the data path from
the memory to the register file usually does not go through
the ALU, so no chance to set the flags.
More information about the Oberon