[Oberon] RISC5: memory instructions and flags

[Paul Reed]

Hi Hellwig,

On 2021-02-06 12:46, Hellwig Geisse wrote:
> This document doesn't say anything about setting the condition
> flags when executing memory instructions... May the compiler rely on 
> the fact that
> the condition flags are set on a load?

Sorry that this has caused you trouble. There's another gotcha here, 
that although the "co-optimised" version of the Verilog/Lola and the 
compiler allow the shorter code sequence when testing the result of a 
load, it doesn't work in all branch cases, because the C and V flags are 
*not* set.

So you're right, if you have your own RISC implementation it might make 
sense to stick to the "pure" RISC ideal of only ALU ops set flags, and 
not also optimise the load code.

Cheers,
Paul