[Oberon] RISC5: memory instructions and flags
hellwig.geisse at mni.thm.de
Sat Feb 6 15:35:47 CET 2021
thanks for your answer.
On Sa, 2021-02-06 at 13:53 +0000, Paul Reed wrote:
> Sorry that this has caused you trouble.
No trouble at all - only an interesting morning... :-)
I'm happy that the error messages coming from my memory test
program didn't have anything to do with a dysfunctional SDRAM
controller, but were caused by details of setting the flags.
> There's another gotcha here,
> that although the "co-optimised" version of the Verilog/Lola and the
> compiler allow the shorter code sequence when testing the result of a
> load, it doesn't work in all branch cases, because the C and V flags are
> *not* set.
It seems questionable anyway how carry and overflow flags
should be set on a load, as there is no arithmetic involved.
More information about the Oberon