[Oberon] RISC5: memory instructions and flags

Hellwig Geisse hellwig.geisse at mni.thm.de
Sat Feb 6 16:03:51 CET 2021

On Sa, 2021-02-06 at 15:21 +0100, Joerg wrote:
> I have a different view:
> For me the C and V flags are results of the ALU calculation as C and V need TWO operands.
> But the N and Z flags can be set whenever a register is changed, as they only need ONE operand,
> (eg the result of a load or depositing the link address in a register)
> So, I would vote to adopt the RISC documentation.

There is a (week) argument in favor of not touching the flags
during memory instructions: the compiler could delay branches
on a result while loading the next part of data to operate on.

The old microprocessors of around 1980 were very careful
in defining the setting of C and Z flags, so that these
flags could be used to transmit boolean results in parallel
to a function result. Data move instructions (even if they
were register-to-register moves) never changed any of the
flags. This however is not relevant here, as the RISC5 MOV
instructions set N and Z flags anyway.


More information about the Oberon mailing list