[Oberon] Emulating interrupts in oberon-risc-emu as in the RISC5 specification

Charles Perkins chuck at kuracali.com
Tue Mar 30 23:45:07 CEST 2021

Hello Everybody,

I wanted to explore interrupt handling in Oberon and I discovered that
Peter De Wachter's excellent emulator did not implement them, which is not
surprising, as the current Project Oberon source doesn't use them as far as
I can tell and the only example source code showing how to use interrupts
is the TestInt module on Professor Wirth's own 2018 update to RISC5:

Since I wanted to compile and run that small example I forked Peter's
emulator and added support for Interrupts in a branch here:
https://github.com/io-core/oberon-risc-emu (only a few small changes were

With those changes I am able to compile the TestInt module and execute it
in the emulator using the 2019 disk image in the repo. Emulated LEDs update
once per second as expected.

I don't intend to maintain a fork of Peter's emulator, I just wanted to
experiment with interrupts and share the implementation in case anyone else
is interested.

Best Regards,
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