[Oberon] Stimulus driven interrupts?
jmaggio14 at gmail.com
Thu May 6 22:19:27 CEST 2021
Gray - that would be fantastic! I'd love to look more into it
Jorg - thank you, that module simplifies things a lot. Would it be
possible for you to walk me through how it works in more detail? I'm
not following every line - for instance what does SYSTEM.LDPSR do?
Adding to Jörg's post, below, I have a simple eight channel interrupt
controller in the FPGA hardware as "front end" to the single interrupt
of the RISC5 CPU, including the corresponding Oberon driver of course.
It adds one clock cycle of latency, IIRC. Let me know if you're
interested. It requires some minor changes to the RISC5 CPU, though.
> -- gray
On Thu, 6 May 2021, at 19:53, Joerg wrote:
> >* Hi Jeff
> >* The interrupt signal is handed over by the HW to the RISC5 CPU in RISC5Top.v.
> >* The interrupt signal in the CPU is called .irq, and the current RISC5Top.v hands over periodic interrupts with the Verilog code below
> >* RISC5 riscx(.clk(clk), .rst(rst), *.irq(limit),*
> *>* .rd(rd), .wr(wr), .ben(ben), .stallX(vidreq),
> >* .adr(adr), .codebus(codebus), .inbus(inbus),
> >* .outbus(outbus));
> > >* assign limit = (cnt0 == 24999);
> >* But you are totally free to set the CPU’s .irq signal on other HW conditions, e.g. a packet on the Ethernet board arrived or the temperature sensor says the meat is tender.
> >* Below I attached an older mail on an “simple” API to facilitate programming with interrupts. Instead of Kernel.Install you would call Interrupt.Install to install the interrupt handler.
> >* br
> >* Jörg
-------------- next part --------------
An HTML attachment was scrubbed...
More information about the Oberon