[Oberon] Emulators / Hardware Enumerator

Hellwig Geisse hellwig.geisse at mni.thm.de
Sun Feb 6 23:48:31 CET 2022


thanks for your explanations. Let me just answer one of
your questions.

On So, 2022-02-06 at 14:21 +0100, Michael Schierl wrote:
> SRAM based boards do not use cache. DRAM based boards do, but
> what could software do if it knew about the cache setup?

If I- and D-caches are both present, and do not implement any
cache coherency protocol, you need instructions (for use in
the kernel and possibly in debuggers) to flush the D-cache
and invalidate the I-cache: Think of loading an executable,
which - after loading - sits only in the D-cache, while the
I-cache has old (invalid) instructions cached from the same
addresses where the new program was loaded.

Btw, this is not a hypothetical situation: I recently added
caches to my ECO32 processor, and I promptly ran into this
exact difficulty.


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