[Oberon] Emulators / Hardware Enumerator

[Michael Schierl]

Hellwig,


Am 06.02.2022 um 23:48 schrieb Hellwig Geisse:

> If I- and D-caches are both present, and do not implement any
> cache coherency protocol, you need instructions (for use in
> the kernel and possibly in debuggers) to flush the D-cache
> and invalidate the I-cache.

Fair point, but would that still be the same ISA, if the cache coherency
changes the behaviour and not just the performance? So far, the hardware
enumerator assumes that the ISA is the same RISC5 architecture, just the
peripherals are different.

(Probably it could be made working without changing the instruction set,
by having a special MMIO address that can be written to to flush caches.
And it is fairly simple to emulate that scenario in emulators, by just
providing two copies of RAM, and only synchronizing them on a cache
flush. But all modules that dynamically create and execute code would
need changing, of course, to work on such a machine.)


Regards,


Michael