[Oberon] ALU 2015 and 2018

Skulski, Wojciech skulski at pas.rochester.edu
Tue May 10 00:23:12 CEST 2022


  trying to somewhat understand RISC5, I looked at two implementations dated 25.9.2015 and 31.8.2018. Four questions:

1. Is the latter implementation the most recent one? 

2. The ALU implementation in the latter one looks very significantly different from the former. The former uses the instruction mnemonics like MOV, LSL, etc., as explained in RISC.pdf on page 9. The latter one does not use any mnemonics. It is a cascaded case statement (or a priority decoder, if you will) whose coding style looks mind boggling to me. Why is it so that the coding style was changed so significantly?

3. Almost all the RISC5.v (either version) is coded combinatorially with "assign" statements. There is only one clocked "always block" at the end, where it is not even clear how these combinatorial paths get executed. For example, the ALU result "aluRes" is never assigned to any register, as one would expect in a register-based FPGA design. In the RISC5 design, instruction execution looks almost like a byproduct. How was this design motivated, when it it is generally believed in the FPGA literature that registers are the most fundamental bulding blocks of any FPGA firmware?

4. Looking at the "assign" equations (especially the ALU) I suspect that they created long combinatorial paths which slow down the CPU operation. Is it true? Can the CPU run faster if it was explicitly coded with registers? Or is Xilinx compiler smart enough to automatically infer the registers by itself? 

Thank you,

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