[Oberon] ALU 2015 and 2018

[Paul Reed]

Hi Wojtek,

>   trying to somewhat understand RISC5, I looked at two implementations
> dated 25.9.2015 and 31.8.2018... Is the latter ... the most recent one?

Yes. Prof. Wirth's news file

http://people.inf.ethz.ch/wirth/news.txt

contains only some subsequent changes to the Lola code, to bring things 
into line somewhat. You may find the Lola code easier to understand:

http://people.inf.ethz.ch/wirth/Lola/index.html


> ... The ALU implementation in the latter one looks very significantly
> different from the former

This was indeed done to shorten or balance some of the combinational 
paths.


> 3. Almost all the RISC5.v (either version) is coded combinatorially
> with "assign" statements. There is only one clocked "always block" at
> the end, where it is not even clear how these combinatorial paths get
> executed.

Nothing gets "executed", it's a definition of hardware. Everything 
happens at the same time, as described. And I disagree, I find this 
style rather easier and simpler than most of the (System)Verilog out on 
the web (and commercial code is even worse, in my experience).


> For example, the ALU result "aluRes" is never assigned to
> any register...

It gets assigned back to the destination register, port .din() of the 
Registers module, via regmux, if regwr is active.


> ... Can the CPU run faster if it was explicitly
> coded with registers?

If it was pipelined, yes. But then it would be more complicated. Have a 
look at implementations of RISC-V to see how this is done.


> Or is Xilinx compiler smart enough to
> automatically infer the registers by itself?

No, thank goodness.

HTH,
Paul