[Oberon] RISC5 CPU implementation of 2015 and 2018

[Skulski, Wojciech]

All:

I am repeating this message because the previous one somehow disappeared.

I am  trying to somewhat understand RISC5.v. I looked at two implementations dated 25.9.2015 and 31.8.2018. A few questions:

1. Is the latter implementation the most recent one?

2. The ALU implementation in the latter one looks very significantly different from the former. The former uses the instruction mnemonics like MOV, LSL, etc., as explained in RISC.pdf on page 9. The latter one does not use any mnemonics. It is a cascaded conditional statement (a priority decoder) whose coding style looks mind boggling to me. Why was the coding style changed so significantly?

3. Almost all the RISC5.v (either version) is coded combinatorially with "assign" statements. There is only one clocked "always block" at the end. It is not clear how these combinatorial paths get executed because they are absent from the clocked block. For example, the ALU result is assigned to a combinatorial wire "aluRes" rather that to a  register. How was this design motivated, when it it is generally believed in the FPGA literature that registers are the most fundamental bulding blocks of any FPGA firmware?

4. Looking at the "assign" equations (especially the ALU) I suspect that they created long combinatorial paths which slow down the CPU operation. Is it true? Can the CPU run faster if it was explicitly coded with registers? Or is Xilinx compiler smart enough to automatically infer the registers by itself?

Thank you,
Wojtek