[Oberon] Compiler Construction PDF error

Mon Mar 28 15:09:20 CEST 2022

Ah, I didn't think to look at the source code on the site which would have
been the last word.
 Many thanks.

All the best.

John

On Mon, 28 Mar 2022 at 11:00, <oberon-request at lists.inf.ethz.ch> wrote:

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>    1. Compiler Construction on projectoberon.net (John Stout)
>    2. Re: Compiler Construction on projectoberon.net (Chris Burrows)
>    3. Re: Compiler Construction on projectoberon.net (Joerg)
>    4. Re: Compiler Construction on projectoberon.net (Chris Burrows)
>
>
> ----------------------------------------------------------------------
>
> Message: 1
> Date: Sun, 27 Mar 2022 11:07:43 +0000
> From: John Stout <cuspcomputers at gmail.com>
> To: oberon at lists.inf.ethz.ch
> Subject: [Oberon] Compiler Construction on projectoberon.net
> Message-ID:
>         <
> CAE7M_X1Z_QJpjVft+pGexpLpaq7FggUYgJNA4YfWtv4zHwLanA at mail.gmail.com>
> Content-Type: text/plain; charset="utf-8"
>
> Hello everyone
>
> I'm working on a compiler and emulation of the RISC processor detailed in
> the latest (?) edition of Compiler Construction by Professor Wirth
> from CompilerConstruction1.pdf
> (projectoberon.net)
> <
> http://www.projectoberon.net/wirth/CompilerConstruction/CompilerConstruction.pdf
> >
> .
>
> I can't follow the Oberon code for the emulator in section 9.5 in the
> section handling memory instructions, which differs from Peter De Wachter's
> Oberon RISC emulator at https://github.com/pdewacht/oberon-risc-emu.git
>
> In Compiler Construction, once an instruction has been decoded as a memory
> instruction the address is calculated using
>
> adr := (R[b] + IR MOD 100000H) DIV 4;
>
> which (apart from the DIV 4) agrees with the code in oberon-risc-emu (which
> also sign extends the offset before adding it).
>
> If adr >= 0 then a load is carried out, and the N and Z flags set depending
> on the value loaded.
> However (and this is the bit I don't understand) if adr < 0 then a store is
> carried out, whereas in oberon-risc-emu u bit of the instruction is checked
> and if 0 a load is carried out and if 1 a store is carried out.
>
> Since I know oberon-risc-emu works, and that agrees with the settings for
> the u and v bits in Compiler Construction then I assume that must be the
> correct implementation, but is there an error in Compiler Construction or
> am I missing something very simple?
>
> All the best.
>
> John Stout
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> ------------------------------
>
> Message: 2
> Date: Sun, 27 Mar 2022 22:40:38 +1030
> From: Chris Burrows <cfbsoftware at gmail.com>
> To: ETH Oberon and related systems <oberon at lists.inf.ethz.ch>
> Subject: Re: [Oberon] Compiler Construction on projectoberon.net
> Message-ID:
>         <CALmD50XNnbeRmA=vEoW_5WieKD=
> 3u3mXoNy9CW4aq0c+sS6rUw at mail.gmail.com>
> Content-Type: text/plain; charset="utf-8"
>
> On Sun, Mar 27, 2022 at 9:38 PM John Stout <cuspcomputers at gmail.com>
> wrote:
>
> > Hello everyone
> >
> > I'm working on a compiler and emulation of the RISC processor detailed in
> > the latest (?) edition of Compiler Construction by Professor Wirth from
> CompilerConstruction1.pdf
> > (projectoberon.net)
> > <
> http://www.projectoberon.net/wirth/CompilerConstruction/CompilerConstruction.pdf
> >
> > .
> >
> > I can't follow the Oberon code for the emulator in section 9.5 in the
> > section handling memory instructions, which differs from Peter De
> Wachter's
> > Oberon RISC emulator at https://github.com/pdewacht/oberon-risc-emu.git
> >
> > In Compiler Construction, once an instruction has been decoded as a
> memory
> > instruction the address is calculated using
> >
> > adr := (R[b] + IR MOD 100000H) DIV 4;
> >
> > which (apart from the DIV 4) agrees with the code in oberon-risc-emu
> > (which also sign extends the offset before adding it).
> >
> > If adr >= 0 then a load is carried out, and the N and Z flags set
> > depending on the value loaded.
> > However (and this is the bit I don't understand) if adr < 0 then a store
> > is carried out, whereas in oberon-risc-emu u bit of the instruction is
> > checked and if 0 a load is carried out and if 1 a store is carried out.
> >
> > Since I know oberon-risc-emu works, and that agrees with the settings for
> > the u and v bits in Compiler Construction then I assume that must be the
> > correct implementation, but is there an error in Compiler Construction or
> > am I missing something very simple?
> >
> > All the best.
> >
> > John Stout
> >
>
> Have a closer look. In Compiler Construction the test for load / store is
> NOT based on the sign of adr, it is based on one of the following
> equivalent tests:
>
> IF ~ODD(IR DIV 20000000H)  (* in the book *)
>
> or
>
> IF ~ODD(ASH(IR, -29)) (* in the accompanying source code *)
>
> --
> Regards,
> Chris Burrows
> CFB Software
> https://www.astrobe.com/RISC5
> -------------- next part --------------
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>
> ------------------------------
>
> Message: 3
> Date: Sun, 27 Mar 2022 14:48:04 +0200
> From: Joerg <joerg.straube at iaeth.ch>
> To: ETH Oberon and related systems <oberon at lists.inf.ethz.ch>
> Subject: Re: [Oberon] Compiler Construction on projectoberon.net
> Message-ID: <E733A707-C6CA-46FC-A43A-F2CBB38B36BF at iaeth.ch>
> Content-Type: text/plain; charset="utf-8"
>
> John
>
> there is indeed an error in chapter 9.5 of the pdf you linked.
>
> If you read bullet 3 in the intro to chapter 9.5 a distinction of adr>= 0
> and adr<0 is mentioned for the memory mapped IO. But as mentioned in the
> intro, memory mapped IO is not implemented. For a fully working emulator
> you will need this IF adr>=0 and IF adr<0.
> But for this reduced mini emulator code in chapter 9.5, this IF is wrong
> (most probably a leftover of the full code). Take the sample code Chris
> provided.
>
> br
> J?rg
>
> > Am 27.03.2022 um 14:11 schrieb Chris Burrows <cfbsoftware at gmail.com>:
> >
> > ?
> >> On Sun, Mar 27, 2022 at 9:38 PM John Stout <cuspcomputers at gmail.com>
> wrote:
> >
> >> Hello everyone
> >>
> >> I'm working on a compiler and emulation of the RISC processor detailed
> in the latest (?) edition of Compiler Construction by Professor Wirth from
> CompilerConstruction1.pdf (projectoberon.net).
> >>
> >> I can't follow the Oberon code for the emulator in section 9.5 in the
> section handling memory instructions, which differs from Peter De Wachter's
> Oberon RISC emulator at https://github.com/pdewacht/oberon-risc-emu.git
> >>
> >> In Compiler Construction, once an instruction has been decoded as a
> memory instruction the address is calculated using
> >>
> >> adr := (R[b] + IR MOD 100000H) DIV 4;
> >>
> >> which (apart from the DIV 4) agrees with the code in oberon-risc-emu
> (which also sign extends the offset before adding it).
> >>
> >> If adr >= 0 then a load is carried out, and the N and Z flags set
> depending on the value loaded.
> >> However (and this is the bit I don't understand) if adr < 0 then a
> store is carried out, whereas in oberon-risc-emu u bit of the instruction
> is checked and if 0 a load is carried out and if 1 a store is carried out.
> >>
> >> Since I know oberon-risc-emu works, and that agrees with the settings
> for the u and v bits in Compiler Construction then I assume that must be
> the correct implementation, but is there an error in Compiler Construction
> or am I missing something very simple?
> >>
> >> All the best.
> >>
> >> John Stout
> >
> > Have a closer look. In Compiler Construction the test for load / store
> is NOT based on the sign of adr, it is based on one of the following
> equivalent tests:
> >
> > IF ~ODD(IR DIV 20000000H)  (* in the book *)
> >
> > or
> >
> > IF ~ODD(ASH(IR, -29)) (* in the accompanying source code *)
> >
> > --
> > Regards,
> > Chris Burrows
> > CFB Software
> > https://www.astrobe.com/RISC5
> >
> > --
> > Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
> > https://lists.inf.ethz.ch/mailman/listinfo/oberon
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> ------------------------------
>
> Message: 4
> Date: Mon, 28 Mar 2022 09:26:02 +1030
> From: Chris Burrows <cfbsoftware at gmail.com>
> To: ETH Oberon and related systems <oberon at lists.inf.ethz.ch>
> Subject: Re: [Oberon] Compiler Construction on projectoberon.net
> Message-ID:
>         <
> CALmD50U+mHAZ3OLZJZkM4F6ChFOss9yVN9ZSdPfeL-K4afoAyg at mail.gmail.com>
> Content-Type: text/plain; charset="utf-8"
>
> On Sun, Mar 27, 2022 at 11:18 PM Joerg <joerg.straube at iaeth.ch> wrote:
>
> > John
> >
> > there is indeed an error in chapter 9.5 of the pdf you linked.
> >
> > If you read bullet 3 in the intro to chapter 9.5 a distinction of adr>= 0
> > and adr<0 is mentioned for the memory mapped IO. But as mentioned in the
> > intro, memory mapped IO is not implemented. For a fully working emulator
> > you will need this IF adr>=0 and IF adr<0.
> > But for this reduced mini emulator code in chapter 9.5, this IF is wrong
> > (most probably a leftover of the full code). Take the sample code Chris
> > provided.
> >
> > br
> > J?rg
> >
>
> Thanks J?rg.
>
> The complete sample code that I was referring to is the file RISC.Mod on
> Prof Wirth's site:
>
> http://people.inf.ethz.ch/wirth/CompilerConstruction/index.html
>
> The sample code that I quoted from the book was mistakenly taken from the
> earlier (2013) revision of the book that I have on my computer rather than
> the updated (2017) version on the website. I apologise for any confusion,
>
> --
> Regards,
> Chris Burrows
> CFB Software
> https://www.astrobe.com/RISC5
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