[Oberon] ALU 2015 and 2018

[Joerg]

Memory access is not in RISC5.v but in RISC5Top.v. There is also the place to add a cache if needed. eg for DRAM.

br
Jörg

> Am 10.05.2022 um 21:23 schrieb Skulski, Wojciech <skulski at pas.rochester.edu>:
> 
> Magnus:
> 
> one of the reasons I am trying to understand RISC5.v a bit better is that I want to use the ZBT memory, whose timing is different from ASRAM. It would be great if RISC5 instruction timing was compatible. I was trying to understand whether it was compatible or not.
> 
> I also want to know where and how I can extend the address from 24 bits to more bits, if I need to. Blindly changing "23" to some other number may or may not do the trick. It would be good to know which "23" should be changed and why.
> 
> As a small example, I discovered that "assign disp = IR[21:0];" in 2018 used to be "assign disp = IR[23:0];" in 2015. This change was made without any comment in the code. This is probably an example why it is crucial to know, which "23" means what and why. This investigation is quite interesting.
> 
> I do not quite agree with PR assessment that this code is easy. It is definitely easy for the authors, but not to myself. I spent a couple days trying to disentangle various details. The result of my unfinished investigation is attached. 
> 
> I have to do all this because we are about to hire a Summer intern to work on this project. This guy would be lost if I handed over the uncommented code. The kind of detail which you see in the attached top level is absolutely crucial for handing over the work to someone else, at least here at the East Coast.
> 
> Thank you for the comments!
> 
> Wojtek
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