[Oberon] ALU 2015 and 2018

[Skulski, Wojciech]

Joerg:

>Memory access is not in RISC5.v but in RISC5Top.v. 

IMHO this is only partly true. I do agree that memory is connected at the top level. But the memory signals are derived inside the CPU, like muxing the inbus, outbus, or address. Also the read and write strobes are derived in the CPU code. The timing between these signals follows from their assignments, which happens inside the CPU. Looking at this code I cannot figure out the timing sequence, because almost all signals are "wires" assigned in the combinatorial section. Those assignments are static. There is no clocked relationship among the wires. 

Those few registers under the "always" block do not bear any clear relation to the memory signals. To me the internal timing among the CPU signals is a mystery. I do not know how it follows from anything I can see in the one and the only "always" block.

My experience with VHDL taught me that the sequential assignments among registers can be easily found in the clocked "process" code. I am pretty sure that the clocked "always" in Verilog is an exact equivalent of the clocked "process" in VHDL. So it is not the language which makes it difficult to infer the timing sequence among the signals. It is rather the way this Verilog was written that makes the timing less than obvious.

> There is also the place to add a cache if needed. eg for DRAM.

I am far away from this topic yet.

Thank you,
Wojtek