[Oberon] ALU 2015 and 2018
skulski at pas.rochester.edu
Wed May 11 03:30:42 CEST 2022
>This scenario is called a two-stage pipeline: two instructions are
>"in flight" within the CPU at any point in time.
I admit that I do not see how this follows from RISC5.v code. There are just four lines under the clocked "always" block, reproduced below. (The next line deals with DIV/MULT, and a few others with the interrupt.) I just cannot see how your statement can be inferred from the following lines of code. The comments in the code are mine.
I gather that the ALU and the Control Unit are two state machines which work in parallel. I cannot see how their mutual timing follows from the "always block" statements. I cannot see how the cascaded ALU statements get executed by the code below, which is the only clocked code in the entire RISC5.v. I cannot see how the timing relationship between the CU and the ALU is related to the code. Could you please elucidate?
always @ (posedge clk) begin
// Both the Instruction Register and the Program Counter belong to the Control Unit.
PC <= pcmux; // load Program Counter from one of many possible sources
IR <= stall ? IR : codebus; // load instruction register from codebus when CPU is not stalled
stallL1 <= stallX ? stallL1 : stallL0;
N <= nn; Z <= zz; C <= cx; OV <= vv;
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