[Oberon] ALU 2015 and 2018
hellwig.geisse at mni.thm.de
Wed May 11 01:25:34 CEST 2022
On Di, 2022-05-10 at 08:21 -0700, Magnus Karlsson wrote:
> The RISC5 cpu is non-pipelined -normally each instruction takes one
> clock cycle to complete, and in the same cycle the next instruction is
this is not quite right. Let's discuss a non-LD/ST, non-MUL/DIV
instruction. It takes one clock cycle to get it from memory into
the instruction register and another one to execute it and store
the result into the destination register. So a single instruction
needs two clock cycles to complete (this is the instruction latency).
You are right in noting that execution of an instruction and fetching
the next one are overlapping: the machine executes one instruction
per clock cycle (this is the instruction throughput).
This scenario is called a two-stage pipeline: two instructions are
"in flight" within the CPU at any point in time.
More information about the Oberon