[Oberon] ALU 2015 and 2018

Paul Reed paulreed at paddedcell.com
Wed May 11 14:23:32 CEST 2022

Hi Hellwig,

> do we agree that "normal" instructions (not LD/ST, not MUL/DIV)
> have a latency of two clock cycles

Thanks for your efforts to clarify, but no; I think you could argue it's 
one-cycle latency though.

Without wanting to sound like Humpty Dumpty I think we need to be very 
careful what we mean. :)

I'm not sure you can use standard definitions when applied to RISC5, 
because of its asynchronous nature, but in answer to

> What, then, is your exact definition of a two-stage pipeline?

I'll have a go:

Where the next instruction has been fetched and is held in the CPU, 
being decoded, in parallel with the execution phase of the current 
instruction; and the next instruction after that (which may need to be 
discarded) is being fetched.

My point is, in RISC5 the next instruction arrives only just in time, at 
the end of the cycle, can't be decoded yet, and is never discarded. The 
former is why I think the design would need a thick coat of looking at 
in order to get it to interface with synchronous memory. It may also be 
why Wojtek is looking for parallelism which simply isn't there.


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