[Oberon] ALU 2015 and 2018

Hellwig Geisse hellwig.geisse at mni.thm.de
Wed May 11 13:52:13 CEST 2022

Hi Paul,

On Mi, 2022-05-11 at 12:02 +0100, Paul Reed wrote:
> So I agree with Magnus - it's kind of not pipelined at all, really.

do we agree that "normal" instructions (not LD/ST, not MUL/DIV)
have a latency of two clock cycles, while the throughput, given
a sequence of these instructions, is one instruction/clock cycle?

If the machine wasn't pipelined at all, the throughput would be
the reciprocal of the latency, 0.5 instructions/clock cycle.

Perhaps we have different definitions of "pipelined". What,
then, is your exact definition of a two-stage pipeline?

Best regards,

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