[Oberon] ALU 2015 and 2018

[Hellwig Geisse]

Jörg,

On Mi, 2022-05-11 at 19:51 +0200, Jörg wrote:
> 
> I think you are not right. Registers.v uses the the primitive RAM16X1D.
> This XILINX primitive does something different in the first halve of the clock than in the second
> halve.
> This is a dual port ram. The first port is used to read and write, the second port is only for
> read.
> In the first halve it writes the result from the previous instruction and in the second halve it
> reads the registers for the current instruction.
> 

I admit that this brings an additional complication into
the picture. This "write-before-read" behavior is normally
used to avoid a separate forwarding unit, needed to ensure
that the result of a computation can be used *and* written
to its destination register in the same clock cycle. This
would be the case, e.g., if an instruction writes to register
n and the next instruction (already fetched) wants to use
the new contents of register n as one of its operands.

I doubt however that this changes any aspect of the
fundamental pipeline, but who knows...

I should stick to my own advice and write a faithful
simulation of the beast, then these questions could
be answered easily.

Hellwig