[Oberon] ALU 2015 and 2018

[Hellwig Geisse]

Wojtek,

On Do, 2022-05-12 at 20:29 +0000, Skulski, Wojciech wrote:
> 
> We just discovered that a computer science professor (Hellwig)
> does not fully understand RISC5 code.

not very flattering, but true. :-)

But I'm working on it. You can follow my efforts here:
https://github.com/hgeisse/THM-Oberon/tree/master/fpga-RISC5/v0
Please note that the code isn't ready for simulation yet.

The original design depends heavily on the assumption that
the hardware synthesizer will set the initial state of all
registers to zero. That of course doesn't happen automatically
in a simulation, which results in very many signals being
"unknown" at the start of the simulation. So I have to retrofit
the modules with proper start conditions (which, btw, would not
have been necessary, if all state elements were properly cleared
on the "rst" signal).

Simulating the architectural registers was easy; I found
a Verilog description (from Xilinx) online.

Main memory (ISSI 256Kx16, 10 ns SRAM) isn't finished yet.

Peripheral devices are essentially non-existent, but are
not needed anyway for answering our questions about the
pipeline.

I will report here when there is a version which can be
executed reasonably.

Hellwig