[Oberon] ALU 2015 and 2018

[Paul Reed]

Hi Wojtek, Hellwig,

> On Do, 2022-05-12 at 20:29 +0000, Skulski, Wojciech wrote:
>> 
>> We just discovered that a computer science professor (Hellwig)
>> does not fully understand RISC5 code.
> 
> not very flattering, but true. :-)
> 
> But I'm working on it...

Anything more than a toy example, in any programming language or HDL or 
anything else for that matter, requires careful study: we can build 
incredible artefacts easily with these powerful tools - it is our cross 
to bear. (And even toy examples can be quite subtle.)

So I think Wojtek's snipe can be safely ignored. But I do think you 
might both be better off understanding (and perhaps simulating) RISC0 
before approaching RISC5. It certainly helped me.

And personally I would rather have a document like [1] than copious 
comments. From experience, I prefer succinct code which only comments 
non-obvious or non-idiomatic potential trip-ups, and then some separate 
architectural description, if someone has taken the time and care to 
write it. So RISC and Project Oberon are perfect for me.

I once had to maintain some code which was so heavily commented that it 
was like reading another program in another language inside the same 
source code file. And of course, comments are never to be trusted. As 
Prof. Wirth says, the programs themselves "alone contain the ultimate 
explanations."

Cheers,
Paul

[1] The Design of a RISC Architecture and its Implementation with an 
FPGA
https://people.inf.ethz.ch/wirth/FPGA-relatedWork/RISC.pdf