[Oberon] [EXT] ALU 2015 and 2018
joerg.straube at iaeth.ch
Fri May 13 14:48:01 CEST 2022
„1“ is described here. Chapter 4
> Am 13.05.2022 um 14:33 schrieb Skulski, Wojciech <skulski at pas.rochester.edu>:
> Andreas wrote:
>> Writing correct code is already demanding enough, but writing publishable (!)
>> code is exacting!
> Publishable? RISC5 has been published. Are you arguing that this code is "publishable" because it was published? Or are you saying this code stands by itself as being publishable because of its clarity? Should this code be presented and taught as is?
> I tried. I fed it to a very bright student (a PhD level in FPGA and EE). I will refrain from publishing his assessment because it was not publishable.
> OK, here is the question concerning the code snipped which I discussed:
> assign pcmux = ~rst | stall | intAck | RTI ?
> (~rst | stall ? (~rst ? StartAdr : PC) :
> (intAck ? 1 : SPC)) : pcmux0;
> What is this number "1" doing here and where is it described and documented well enough such that the student can be left alone to understand what the student is doing w/o further instruction?
> I guess we are seeing here why RISC5 never took off in the teaching community, except in the presence of its authors who obviously know what is going on here. I guess they are alone in that.
> Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
-------------- next part --------------
An HTML attachment was scrubbed...
More information about the Oberon