[Oberon] [EXT] ALU 2015 and 2018

[Joerg]

Wojtek

I strongly assumed that the student or whoever studies RISC5 knows, that RISC5 handles memory as a bunch 32bit words. RISC5 is a 32bit machine.

The document tells you that the interrupt handler sits at memory location 4 (in bytes). This is adress 1 (in words)

br
Jörg

> Am 13.05.2022 um 15:06 schrieb Skulski, Wojciech <skulski at pas.rochester.edu>:
> 
> 
> Wojtek
> 
>> „1“ is described here. Chapter 4
>> https://people.inf.ethz.ch/wirth/ProjectOberon/RISC5.Update.pdf
> 
> Sure I know. I have it opened on my desktop. Could you please cite this text and argue that the student can be left alone with what was written there, without any further instruction?
> 
> Are you saying that I should pay an intern or an engineer for his time spent on discovering what '1" means in this particular place and why it is "1" rather than some other number?
> 
> Are you arguing that I would be a good manager if I handed this code "as is" and its PDF documentation to a new hire and pay government money for this person discovering on his/her own what to do if I asked for modifications to the interrupt mechanism of RISC5, which is a legitimate request, I believe? 
> 
> Wojtek
> 
> 
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