[Oberon] [EXT] ALU 2015 and 2018

[joerg.straube at iaeth.ch]

Wojtek
Just for your info:
I wrote a little wrapper for an easy installation of an interrupt handler.
Jörg
. . . .
MODULE Interrupt; (* jr/7feb20 *)

IMPORT SYSTEM, Kernel;

PROCEDURE* Empty; BEGIN END Empty;

PROCEDURE Install*(handler: PROCEDURE);
                CONST PushR0ontoStack = 0A0E00000H; (* STW R0 SP 0 *)
                VAR instr: INTEGER;
                BEGIN
                               SYSTEM.LDPSR(0);
                               Kernel.Install(SYSTEM.ADR(Empty), 4);
                               SYSTEM.GET(ORD(handler)+4, instr);
                               IF instr = PushR0ontoStack THEN
                                               Kernel.Install(ORD(handler), 4);
                                               SYSTEM.LDPSR(1)
                               END
                END Install;

BEGIN
                Install(NIL)
END Interrupt.

ORP.Compile jr.Interrupt.Mod/s ~
ORTool.DecObj Interrupt.rsc ~


Von: Joerg <joerg.straube at iaeth.ch>
Datum: Freitag, 13. Mai 2022 um 16:04
An: ETH Oberon and related systems <oberon at lists.inf.ethz.ch>
Betreff: Re: [Oberon] [EXT] ALU 2015 and 2018
Wojtek

As can be seen in the Verilog code, Hardware-wise the CPU does a jump to memory location 4.
Software-wise you can decide what you do with this HW capability.
Either you put the code of your interrupt handler there or - the approach the Oberon OS takes - put a jump instruction at location 4 and thus allow to put the interrupt handler whereever you like to put it in memory.

The SW code in chapter 4 explains how to use the interrupt capability. The SYSTEM.PUT is important!

br
Jörg

> Am 13.05.2022 um 15:47 schrieb Skulski, Wojciech <skulski at pas.rochester.edu>:
>
> Joerg:
>
> the code which we discussed should not be defended. It should be rewritten. The number "1" needs to become a parameter. Relocating an Interrupt Service Routine is a legitimate request. Doing this should not require diving into code and finding "1" hidden somewhere w/o a line of comment.
>
>> I strongly assumed that the student or whoever studies RISC5 knows,
>> that RISC5 handles memory as a bunch 32bit words. RISC5 is a 32bit machine.
>> The document tells you that the interrupt handler sits at memory location 4 (in bytes).
>> This is adress 1 (in words)
>
> You also needs to add that RISC5 address is byte-wise rather than word-wise. This should be reiterated in the PDF in this particular place, and also in the comment in the code. Also, "1" should be a localparam rather than a literal.
>
> You would be surprised what students do not know these days. I work with these students all the time. We hire them as interns. We need those guys to be productive, which will not be the case if we throw them into deep water w/o instruction.
>
> If you have someone whom you educated well enough to not require such guidance, then please send this person to me because I need an EE right now. The one who can understand your code will be ideal. This person needs to be authorized to work in the USA.
>
> W.
>
>
> --
> Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
> https://lists.inf.ethz.ch/mailman/listinfo/oberon
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