[Oberon] *****SPAM***** Re: ALU 2015 and 2018

[strohm at airmail.net]

The fundamental issue here would appear to be the adoption into Verilog of the C ternary ("?:") operator, as opposed to finding something more readable.

In the mid-1970s or so, it was not unusual to see conditional expressions expressed in the literature as "if <logical expression> then <value1> else <value2> fi".  It is immediately obvious that this is exactly isomorphic to the ternary operator, but much more readable.

I suspect that, were we to adopt Dijkstra's view that our job is to give the populace what they need, not necessarily what they think they want, and to tell the truth even when it is unpleasant, we would eventually find ourselves telling the world that C was a disaster and C++ an even worse one.  I am, however, not going to hold my breath until any of that happens.
 

--John R. Strohm

On Thu, 12 May 2022 20:29:00 +0000, "Skulski, Wojciech" <skulski at pas.rochester.edu> wrote:
>
> Joerg:
>
>> „Readable“ is a subjective term.
>
> We just discovered that a computer science professor (Hellwig) does not fully understand RISC5 code.
> Neither do I despite 20 years of VHDL experience. This discovery is a disaster for the NW school of thought.
> It directly contradicts all NW ideals. How can RISC5 be ever taught to anyone, if the computer science
> professor has problems with answering some basic questions concerning its architecture?
 



-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.inf.ethz.ch/pipermail/oberon/attachments/20220513/49e1b02b/attachment.html>