[Oberon] ALU 2015 and 2018

[Pablo Cayuela]

Please note that Walter Gallegos start a long discussion with many on the
list, suggesting the use of DCM in the RISC5 Verilog design implemented on
Xilinx FPGAs that gave the block.

You could refer to:
https://lists.inf.ethz.ch/pipermail/oberon/2016/008936.html

Hope that you find that discussion illuminating on related topics of this
new thread.

Walter also published a VHDL version of Risc5 that I could share with you
in case you're interested. Walter was not responding any email in the last
4 years, that's why I offer you the files.

Best regards,
Prof Pablo Cayuela
Argentina

El vie., 13 de mayo de 2022 13:10, Hellwig Geisse <hellwig.geisse at mni.thm.de>
escribió:

> ...
> You will have to use a "global clock buffer" to get clk onto
> the clock tree in order to clock flip-flops with it - maybe
> the synthesizer does insert one automatically. I don't know.
> I for one would use a DCM (digital clock manager); all FPGAs
> offer some variant of these. The statement above works for
> simulation, though... :-)
>
> Hellwig
> --
>
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