[Oberon] Implementing unsigned right shift for Oberon RISC5 machine

Michael Schierl schierlm at gmx.de
Tue Apr 11 21:27:14 CEST 2023


as you may know, Oberon RISC5 machine only has an arithmetic right shift
(extending the sign) and no unsigned right shift (fillingwith zeroes).
For Oberon, that instruction is not needed, but what if you want other
languages to target the architecture?

I was thinking of how to implement it in a concise way

- No loops, as little branching as possible
- Having the count in a register (for a constant it is trivial to emit
   an additional AND to mask the bits), should work for all values from 0
   to 31
- Should work even if the destination is one of the source registers
- As few scratch registers as possible

I came up with this (using two scratch registers R1, R2):

USR Rd, Rs, Rc (destination, source, count) translates to

SUB R1, Rc, 1
B CS move # Rc was zero
ASR Rd, Rs, 1
MOV+U R2, 80000000H
ANN Rd, Rd, R2
ASR Rd, Rs, R1
B done
move: MOV Rd, Rs

Or in case Rd is neither Rs nor Rc, you can get away with only one
scratch register, and the same number of instructions/branches on each path:

ASR Rd, Rs, 1
MOV+U R1, 80000000H
ANN Rd, Rd, R1
SUB R1, Rc, 1
B CS move
ASR Rd, Rs, R1
B done
move: MOV Rd, Rs

Any easier solution I missed?



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