[Oberon] The 2013 Project Oberon System running on RISC-Vinstead of RISC-5
Rochus Keller
me at rochus-keller.ch
Thu Aug 6 11:54:45 CEST 2026
(just noticed that I forgot to "text only", so here the same response with the right format)
@ Michael Engel
Yes, I'm aware of the Baochip and watched a few talks about it. I agree that having an MMU on a
microcontroller is useful for many applications. MMUs are rare in ARM microcontrollers (i learned that
only the Cortex-R82 optionally has one). The new ESP32-S31 seems to have one as well. Though I appreciate that
the Oberon Systems don't need one and are thus very well suited for todays microcontroller boards,
given all required peripherals are provided. Personally I prefer chips and boards with broad and
longterm availability because migrating a system is always a lot of work. The Olimex ESP32-P4-PC
even has a HDMI connector, so it's just plug and play, like the Raspis.
Best regards
Rochus Keller
_______________________________
From: Michael Engel
Sent on: Wed, 05 Aug 2026 23:26:17 +0200
To: ETH Oberon and related systems
Cc:
Subject: Re: [Oberon] The 2013 Project Oberon System running on RISC-Vinstead of RISC-5
@ Rochus
Thanks for summarizing the differences, it's interesting to see the distinct approaches – I definitely have to try your port!
Another interesting platform for Oberon on RISC-V might be Andrew "bunny" Huang's Baochip, an open source RV32
SoC running at 350 MHz (with an sv32 MMU!) with 4 MiB of non-volatile ReRAM and 2 MiB of SRAM. In addition, the
chip features four additional 700 MHz RV32 cores which can be used to implement peripheral interfaces and protocols
in software, somewhat like a very much extended version of the Raspberry Pi Pico's PIO programmable state machines
(this could be used to enable VGA output, PS/2 input and ideally some form of network).
I just received two of the boards: https://www.baochip.com/
The whole SoC design is open hardware, so with Oberon one could build a complete open source system. I think this
comes close to Niklaus Wirth's original ideas for his RISC5 system in Project Oberon 2013. I'm very much tempted to
try to port Rikke's system to the Baochip in my upcoming vacation...
Working with Rikke on her Oberon project was a fun and sometimes pretty crazy; it was great to discuss Rikke's progress
and ideas, often for hours each week (though unfortunately mostly online due to Covid back then).
Rikke also used her RISC-V port and knowledge to improve the system even further. We were wondering what the
minimum amount of memory would be that allowed to run the Oberon system with compiler and GUI. For this, Rikke
took an old idea, memory overlays, and adapted it to work with Oberon.
This code is also online at https://github.com/solbjorg/oberon-riscv-overlays
and Rikke's thesis is available from https://nva.sikt.no/registration/0198eaa55f73-810e68fe-af02-45b4-813b-90c006bc0603
Best,
Michael
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