[Oberon] What is the status of Lola-2 and its use in the FPGA version ofProject Oberon?

Skulski, Wojciech skulski at pas.rochester.edu
Fri Mar 15 05:37:55 CET 2019


only Paul knows. I can only speak from my experience.

>> I am constantly surprised that PO was implemented in C-like Verilog
>> rather than Pascal-like VHDL.

> I'm only guessing / speculating but:
> 1. Easier to compile to a lower-level language?

Neither Verilog nor VHDL are compiled in the programming sense. They are both translated in a series of steps until finally the resulting netlist is fit into the FPGA by simulated annealing. I suspect/know/believe that by the time it happens all the differences between both representations are long gone.

> 2. Not so much to be gained translating from one language to another that is
> very similar? i.e. There is less need to try to make VHDL more palatable.

With a bit of effort both languages translate between themselves one-to-one. An evidence is provided by the books by Pong P. Chu, who published two parallel versions of the same designs. See RiskFive.com for the book titles. 

Moreover, Xilinx tools support mixed projects, where some files are in Verilog while others are in VHDL. It proves a very high level of compatibility between the two.

The Verilog/VHDL chasm is rumored to be a communal thing. The ASIC designers tend to use Verilog, while the FPGA programmers tend to use VHDL. Most Xilinx app notes were using VHDL. Very few used Verilog. The Open Cores community seems to be the other way around. 

Finally, the modern Verilog style is System Verilog rather than Verilog. The newest book by Pong P. Chu has System Verilog in its title. The difference between classic Verilog and System Verilog is like K&R C versus ANSI C. Who is using K&R C these days? Likewise, why use the old Verilog if System Verilog is just better? See the said books for the discussion.


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