[Oberon] What is the status of Lola-2 and its use in the FPGA version ofProject Oberon?
joerg.straube at iaeth.ch
Fri Mar 15 09:08:21 CET 2019
> Neither Verilog nor VHDL are compiled in the programming sense. They are both translated in a series of steps until finally the resulting netlist is fit into the FPGA by simulated annealing.
Conceptionally, I can not detect a difference between the approch the „synthesizing tool“ (hopefully I used the right wording) and a optimizing multi-pass compiler.
The first step of a multi-pass compiler is syntax analysis, then bring the source in an intermediate representation, then generate code for this representation, then optimize the code in different iterations. This optimization step can even move code blocks around to find the optimal arrangements of assembler code.
In PO a simpler one-pass compiler is used, with only minimal optimization.
> Moreover, Xilinx tools support mixed projects, where some files are in Verilog while others are in VHDL. It proves a very high level of compatibility between the two.
I don‘t understand your argument: Are you saying because the output is the same the input must be similar?
A guy from Hungary and one from England are visiting China. Only because both speak Chinese it does not mean that Hungarian and English are similar.😊
> Likewise, why use the old Verilog if System Verilog is just better?
It depends what you define „better“. The discussions we had in this forum „why use the old Oberon-2 if Oberon-07 is better“ was exactly the same discussion. Some people want to have Oberon-2 back as a lot of code exists. Other say Oberon-07 is leaner and cleaner and therefore preferred...
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