[Oberon] What is the status of Lola-2 and its use in the FPGA version of Project Oberon?

Pablo Cayuela pablo.cayuela at gmail.com
Sat Mar 16 17:19:23 CET 2019

@R. K. <rochus.keller at bluewin.ch>
Just for the sake of clarity:

Hardware Compilation in that article ("286.ps") is a process to translate
experimental subset of Oberon (Oberon-00), that only deals with boolean and
integer data types for variables, and for structured constructions only the
assignment, if and while.
That experimental small language translates to a Lo(gic)La(nguage) tree
structure ("236.ps"), a mature educational framework for teaching classes
on digital design then.
Then with LoLa Tools you can simulate ("215.ps") the resulting circuit that
implements your program written in Oberon-00.

In summary:
Oberon-00  ->   LoLa tree structure  -> LoLa Simulation

With software Trianus and Hades and others related, also from in ETHZ, you
could map graphic&manually ("198.ps" and others) to an FPGA of the old open
structure 6000 (Xilinx, Atmel, etc.), and check if it matches to a LoLa
description that you previously written as a model. Just the same method
that is used today for VLSI and IC-layout. In summary:

FPGA Layout    ->   Layout LoLa tree  = equivalent? =  Description LoLa
tree    <-    LoLa description (text)

Some references about that tools:







All of the software tools work in Oberon versions of around 2000's for
workstation including DOS & Windows PCs. I didn't have 6000 FPGA at the
time, then I only simulates with LoLa tools in Project Oberon for Windows
and DOS.

In summary, LoLa-1 was not about the behavioral description of hardware but
structural; that was the hardware compilation experiment with a traditional
computer programming language translated to hardware. At least that's what
I know about it.

Thanks to your questions I'm rediscovering all the material, I have only
printed versions in my archives, till now, and now everyone of you could
read too. And if any of you continue with the experiments or recreate it,
please let us know!

Pablo Cayuela

On Sat, Mar 16, 2019 at 8:08 AM rochus.keller at bluewin.ch <
rochus.keller at bluewin.ch> wrote:

> @Wojciech Skulski
> Thanks for the document.
> Here are two links that might also help to illustrate your argument:
> https://www.vlsifacts.com/different-coding-styles-verilog-language/
> https://www.researchgate.net/publication/3646848_Behavior_to_structure_using_Verilog_and_in-circuit_emulation_to_teach_how_an_algorithm_becomes_hardware
> Here is yet another link to an article I got from Pablo which illustrates
> what was intended by Lola-1 (presumably in contrast to Lola-2):
> http://citeseerx.ist.psu.edu/viewdoc/summary?doi=
> Best
> R.
> --
> Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
> https://lists.inf.ethz.ch/mailman/listinfo/oberon
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