[Oberon] LolaCreator: a Lola-2 IDE based on Qt Creator

Paul Reed paulreed at paddedcell.com
Fri Mar 22 12:50:37 CET 2019

> ... I assume that it is much more predictable what comes
> out of Yosys when the input is Lola-2 instead of Verilog

No I don't think that's a good assumption, as it happens.  The tools are 
complex in their behaviour.  (Just my experience!)

Hi Walter, EDIF could also be used, sure.  But as to "why" Verilog was 
used as the output in Lola-2, it's just pragmatic, I think.  See Prof. 
Wirth's explanations.  You could output EDIF if you wanted to fairly 
easily, I'm sure.  But it would be more fiddly, and for no particular 
advantage since it's still at the synthesis level, as R. has pointed 
out.  (And there might be some random tool which accepted Verilog, but 
not EDIF.)


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