[Oberon] SDRAM performance

Joerg joerg.straube at iaeth.ch
Fri Nov 15 08:22:33 CET 2019


The answer to your question depends on the mem chip you chose. Let‘s assume we take this one:

For random access you have to look at tRC in table 11. This is the minimum if you have an optimal memory access controller.
If you have to change not only the row but also the bank, tRRD is even worse.

So all in all: 70 ns seems reasonable for random access. Consecutive burst reads are MUCH faster.


> Am 15.11.2019 um 00:17 schrieb Skulski, Wojciech <skulski at pas.rochester.edu>:
> All:
> It will be good to know how fast is SDRAM in practice. I googled for "sdram access time". I found lots of generic discussions where I could learn all the theory and few conclusions. I also found a few practical estimates. Here are the most relevant finds for the record.
> 1. Good online discussion. 
> http://forum.gadgetfactory.net/topic/1934-sdram-controller-with-consistent-access-time/
> There is a long discussion full of many interesting details, simulations, and corner cases. A good read. At the end of the discussion Matthew Hagerty concluded: "My design lets me read or write a word (16-bits in this case) every 70ns."
> So 70 ns is the number I want to remember for a random fetch or store. Block reads are a different matter which is more related to video. There are many interesting thoughts by Hamster in that discussion concerning how to organize the video with SDRAM.
> 2. A PhD thesis in Electrical Engineering, 175 pages. 
> Shao, Jun, "Reducing main memory access latency through SDRAM address mapping techniques and access reordering mechanisms",
> Dissertation, Michigan Technological University, 2006.
> https://digitalcommons.mtu.edu/etds/72
> Like every dissertation, this one also starts with a background information which is worth reading IMHO.
> Hope it helps,
> Wojtek
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