[Oberon] SDRAM performance

Skulski, Wojciech skulski at pas.rochester.edu
Fri Nov 15 16:29:50 CET 2019

> So all in all: 70 ns seems reasonable for random access. Consecutive burst reads are MUCH faster.

Looking at this discussion and other information sources, I now think that either Cellular RAM or HyperRAM will be the most reasonable choices for future FPGA designs which require substantial memory space. These technologies are less suitable for hard silicon CPUs unless the controllers are integrated into ASICs before hand. In case of the FPGAs the controllers can be retrofitted and/or swapped after the boards are designed.

The best number reported for the HyperRAM is WR/RD = 66/102 ns at CLK = 166 MHz and 1x Latency settings of the chip and the controller. It is on par with SDRAM at much lower implementation hassle. These numbers are claimed by the controller #1 below.

Two HyperRAM controllers which I found thus far:

1) Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM. Very well documented.

2) A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs
  Full source and very simple. Poorly documented (i.e., undocumented on par with the spirit of Oberon).

3) A full AXI bus controller design is also available from Cypress. It is very professionally done with full reports, specs, and everything. It is clearly a great design for great professionals. Not me!

The Cellular RAM video application note with very reasonable documentation for the Digilent Nexys-3 board:

3) https://my.eng.utah.edu/~kalla/index_3710.html
  Scroll to the lines titled "If you want to use the Cellular RAM, Paymon found the following materials". The files are linked right below that line.

Hope it helps.


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