[Oberon] SDRAM performance

Skulski, Wojciech skulski at pas.rochester.edu
Fri Nov 15 22:20:36 CET 2019

>it would need additional time critical part: clock domain crossing
>logic operating between 333 MHz RAM and say 50 MHz CPU/video.
>FIFO of course. BTW, HyperRAM operates at up 166 MHz DDR, rather than 333 MHz.

Note that this was already implemented in the controllers which I referenced in my e-mail.

>In our flagship digitizer we are receiving ADC data at 800 MHz. We also interfaced the GbE PHY using the SGMII running at 1.25 GHz. It was not a lottery. It was a careful design. But it was also lots of work. There is no doubt here.

I should have said "gigabits per second" rather than GHz. I often make this kind of mistake. The gigahertz are half of the gigabits. Sorry for that mistake.


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