[Oberon] FPGA RISC byte access

Joerg joerg.straube at iaeth.ch
Thu Dec 19 18:10:12 CET 2019


assign ben = p & ~q & v & ~stallX & ~stallL1;  // byte enable

If you look at above statement, this boils down to "ben = v".
But "byte enable" is only valid for memory instructions (format F2: p=1,
q=0) and the memory is not used by video (=stallX) and is in the correct
cycle of LDR/STR (stallL1)


-----Original Message-----
From: Oberon <oberon-bounces at lists.inf.ethz.ch> On Behalf Of Skulski,
Sent: Thursday, December 19, 2019 5:07 PM
To: ETH Oberon and related systems <oberon at lists.inf.ethz.ch>
Subject: Re: [Oberon] FPGA RISC byte access


  thank you for the pointer! Yes, I did look at RISC.pdf before sending the
e-mail. Section 3.5 says the following, quoted verbatim:

"The only addition to the processor interface is the signal ben (byte
enable) derived from the modifier bit v in memory instructions."

The words "active high" are missing here too. "Derived from" can mean
anything. Also, in the RISC5 ben was derived from p an q, not from v. So it
is less than clear how this paper refers to RISC5. 

Thank you,
Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems

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