[Oberon] Project Oberon: New Edition

[Alexey Veselovsky]

Verilog files from here
http://www.inf.ethz.ch/personal/wirth/FPGA-relatedWork/index.html is about
earlier RISC version. New language report (
http://www.inf.ethz.ch/personal/wirth/Oberon/Oberon07.Report.pdf) not about
the same language as Project Oberon.

Also there is no common Verilog project about how all modules are
connected. So right we can't reproduce Ceres-4 (from Project Oberon 2013)
on FPGA.

PS. LONGREAL also just alias for REAL type in PO2013 compiler, also there
are undocumented embedded procedures (LED procedure for example):
https://github.com/ilovb/ProjectOberon2013/blob/master/ORBX.Mod#L389

Thanks, Alexey


On Fri, Dec 20, 2013 at 5:42 PM, Chris Burrows <chris at cfbsoftware.com>wrote:

> Yes - it is still a 'work in progress' but the Language Report, CPU
> description and Verilog sources are currently on the other pages of Wirth's
> website:
>
> http://www.inf.ethz.ch/personal/wirth/
>
> There is also an updated version of Compiler Construction book.
>
> LONGINT is just an alias for INTEGER and the complete CASE statement is on
> its way,
>
> A version of Astrobe that supports the FPGA compiler is well underway ...
>
> Regards,
> Chris
>
> Chris Burrows
> CFB Software
> http://www.astrobe.com
>
>
> From: Alexey Veselovsky [mailto:alexey.veselovsky at gmail.com]
> Sent: Friday, 20 December 2013 10:30 PM
> To: ETH Oberon and related systems
> Subject: Re: [Oberon] Project Oberon: New Edition
>
> I think that Project Oberon rev 2013 not complete yet.
>
> For example Annex A1 and Annex A2 (language report and CPU
> description) still not published. Also there are no Verilog sources.
>
>
>
> RISC emulator module still written in Oberon rev 1990 (old CASE semantic
> detected).
>
> Whole system and compiler are written in strange language - it is not
> Oberon
> 1990 nor Oberon rev 2013 (LONGINT and other types that has disappeared in
> Oberon 07/13, but new semantic for CASE that not described even in Oberon
> rev 2013 report).
>
> Also there are some typos, for example in 17.2.4: "From a 15 MHz clock rate
> results a refresh rate of 53.5 frames/s" should be replaced to "From a 25
> MHz clock rate results a refresh rate of 53.5 frames/s".
>
> Also I can't found description for clk25 in XGA Verilog module (what
> difference from clk?).
>
> We discuss Project Oberon 2013 here (in Russian)
> : http://oberspace.dyndns.org/index.php/topic,597.0.html
>
> Thanks, Alexey.
>
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>
>
>
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