[Oberon] FPGA Oberon System synthesis for fourteen different FPGAs

[skulski at pas.rochester.edu]

Oops, I put wrong numbers in the 2nd row in the table. The corrected table
is attached.  Sorry for that.

Wojtek

> I synthesized the FPGA Oberon System (FOS) for fourteen Xilinx FPGAs
> listed in the attached spreadsheet. The goal of this exercise was to
> estimate the FPGA resources taken by the FOS and the predicted
> performance. I did not optimize anything. Just compiled "as is" (almost,
> see below). The good news:
>
> 1. The synthesis suceeded for all the listed targets despite the
> differences among the chips.
>
> 2. I did not have to tweak anything (almost).
>
> 3. The estimated performance in MHz looks decent in the new Artix chips.
>
> 4. The FPGA resources taken by FOS are very reasonable for most of the
> chips, except the original one where the design takes the entire chip, and
> the lowest Spartan-6 which was too small to host the firmware. Otherwise
> there is plenty of room left for other firmware modules.
>
> The "almost" means that I had to remove the hardwired clock location from
> the video module. This location made sense for the Spartan-3 XC3S200, but
> not for the other chips. I also removed the pin location file from the
> project because the pins are specific to a particular chip and the board.
>
> Despite this apparent success, this is just a starting point. There are a
> few synthesis warnings in the original target, which need to be understood
> because this design is supposed to be optimal. In other cases there are
> plenty of synthesis warnings due to dissimilar gate fabric among the FPGA
> families. These need to be understood and addressed.
>
> The FOS appears almost portable, but some adjustments will be needed. Some
> features are tied to Spartan-3. For example, the file Multiplier1.v uses
> the built-in MULT18X18, which is specific to Spartan-3. The synthesis tool
> is smart enough to map it to the newer hardware, so there is no immediate
> problem to address here. The MULT18X18 component can be replaced with the
> DSP slice that is present in the newer chips.
>
> The code is written in terse register-transfer (RTL) Verilog that may be
> hard to follow for casual FPGA developers. It may be tempting to recast
> some sections into easier to follow "behavioral HDL".
>
> Hope it helps,
> Wojtek
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