[Oberon] RISC5 implementation issues.

[Walter Gallegos]

Magnus

"This logic signal /clk/ is then connected to a clock buffer BUFG that 
will feed one of the global clock nets"

My apologies, clk routing is :

The logic clk signal -using general propose routing lines and connection 
matrix- is connected to a clock buffer to be able to be connected to FF 
edge detectors. This is the only way that the tool can address the HDL 
definition.

So, RISC5 use general propose resources to routing a clock signal.

Walter.


El 2016-02-16 a las 16:06, Magnus Karlsson escribió:
> On 2/16/2016 9:22 AM, Walter Gallegos wrote:
>>
>> always @(posedge clk0) clk <= ~clk;
>>
>> "posedge" force the implementation tool to use the clock edge 
>> detection available in each FPGA FF; so, this sentence force the tool 
>> to connect a general purpose interconnection network as FF output is 
>> to the clock distribution tree.
>>
>> And again a signal ( not a clock in the FPGA world ) is used as clock.
>>
>> always @(posedge clk)
>> ....
>> end
>>
>
> No, this is not the way it works.  The tool is smart enough to 
> understand what you really mean and will instantiate the appropriate 
> modules as needed.
>
> In the Pepino case, this is how the clock path looks like (as evident 
> by looking at the fully routed design in Xilinx FPGA Editor):
> The CPU clock signal clk is created by a flip-flop that divides the 
> input clock CLK50M by 2.  This logic signal /clk/ is then connected to 
> a clock buffer BUFG that will feed one of the global clock nets.  The 
> global clock signal is called /clk_BUFG/ and is used every where you 
> use it as a clock in the code, as in the /always @(posedge clk)/ 
> statement.
>
>> And after correct this problems don't forget to modify :
>>
>> assign SRwe0 = ~wr | clk, SRwe1 = SRwe0;
>>
>> Here clk is used as signal, so if clk is a clock must not be 
>> connected to a LUT input.
>>
>
> Again, not a problem.  The tool is smart enough to understand that 
> when you use the signal clk as a logic signal it will use the 
> non-buffered signal /clk/ and not the buffered signal /clk_BUFG/.
>
> Magnus
>
>
>
>
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-- 

Walter Daniel Gallegos
Programmable Logic & Software
Consultoría, Diseño, Entrenamiento.
Montevideo, Uruguay
EMAIL walter at waltergallegos.com
Tel +598 26 23 44 60 | Cel +598 99 18 58 88


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