[Oberon] RISC5 implementation issues.

[Magnus Karlsson]

On 2/16/2016 11:37 AM, Walter Gallegos wrote:
> Magnus
>
> "This logic signal /clk/ is then connected to a clock buffer BUFG that 
> will feed one of the global clock nets"
>
> My apologies, clk routing is :
>
> The logic clk signal -using general propose routing lines and 
> connection matrix- is connected to a clock buffer to be able to be 
> connected to FF edge detectors. This is the only way that the tool can 
> address the HDL definition.
>
> So, RISC5 use general propose resources to routing a clock signal.
>
> Walter.
>

There is absolutely nothing wrong with generating a clock signal like this.
Yes, the output from the flip-flop is routed using general routing 
resources, there is no other option.   But after it's sent through the 
BUFG it's a perfectly legit clock signal.

I have created a small project to demonstrate this, it's available on 
GitHub and it will only take ISE a few seconds to generated a bit file.
*ISE will go through this project without a single warning being 
generated.*  Anyone with ISE experience will tell you that it will 
generate warning for every little detail it will find questionable.

The project is available here: 
https://github.com/Saanlima/Pepino/tree/master/Projects/Pepino_clktest

Magnus
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