[Oberon] Oberon / Linux RISC-V

[Peter Matthias]

Hi all,

since everyone now knows the difference between RISC-V and RISC-5, I 
think it's time to publically announce a public preview of Oberon/Linux 
RISC-V. It is based on the MIPS version. Virtually only three Modules 
needed to be changed --Linux0, OPL and OPC.

It is available here: http://oberon.wikidot.com

To test, you need qemu from here: https://github.com/arsv/riscv-qemu , 
make risv32-linux-user target, compile RCompiler.CompileV from 
OLR.Make.Tool and link the static core via the next MBootLinker command.

It still has lots of bugs but lots of modules compile and work, even 
parts of gadgets.

Regards,
	Peter